1. Field of the Invention
The present invention generally relates to the field of integrated circuits. In particular, the present invention is directed to a method of reducing instantaneous current draw and an integrated circuit made thereby.
2. Background of the Invention
As semiconductor chips are being designed and manufactured with increasing functionality requiring higher power at lower voltages, the current demand aboard these chips is becoming higher and higher. This is particularly true for synchronous designs. As shown in FIG. 1, every clock edge creates a large instantaneous current draw in each timing path due to the edge-triggered elements activating at essentially the same time as one another during each clock cycle. This is illustrated in FIGS. 1A and 1B, which show the profiles 20, 24 of instantaneous current drawn by two timing paths during one clock cycle. While these profiles may be different from one another due to the particular characteristics of the individual paths and the elements triggered, it is seen that the peaks 28, 32 of the instantaneous currents occur very close in time to one another near the beginning of the clock cycle.
Since these current draws are additive, as shown in FIG. 1C when peaks 28, 32 (FIGS. 1A and 1B) occur at the same time, or nearly so, the result is an overall current draw profile 36 having a peak value that is equal to the sum of the peak values of individual profiles, or nearly so. If peaks 28, 32 of current profiles 20, 24 have substantially the same value as one another and occur substantially at the same time, the magnitude of peak 40 of the summation of the two profiles is approximately twice the magnitude of each of the two peaks. FIGS. 1A–C illustrate the state of instantaneous current draw for only two timing paths, so the problem may not appear so dramatic. However, an actual chip includes many timing paths. As can be readily appreciated, when instantaneous current peaks are additive across all of the timing paths, the result is a large overall instantaneous current draw across the chip near the beginning of each clock cycle. The simultaneous switching occurring across multiple timing paths is generally known as “simultaneous switching noise” (SSN) and can be detrimental, e.g., to a power supply due to creation of a large voltage spike at peak current draw.
Approaches used to minimize the effect of SSN include adding power and ground contacts and wiring in order to provide a more robust power distribution system, as well as adding on-chip capacitance. However, as voltages continue to decrease on future technologies, these solutions become more costly due to the valuable silicon area required for their implementation and/or increased packaging costs. Asynchronous circuit design could be used to minimize SSN. However, asynchronous design is not well supported from a design tool perspective. What is needed is a solution to SSN that has minimal impact on silicon area and that is well supported by conventional synchronous design tools.